Testing of programmable logic such as Field Programmable Gate Arrays (FPGA) is a very complex task because all logic elements (configuration latches and programmable resources combined) can attain mind-boggling logic combinations requiring huge amount of test-vectors to test them. So Design For Testability (DFT) designers usually adopt a combination of ad hoc and traditional approaches for achieving maximum testability. Any DFT technique, which helps to determine device status at silicon without much of tester's time, is highly desirable.
Generally a Linear Feedback Shift Register (LFSR) is used for generating a particular signature, which verifies a device's functionality to some extent. An LFSR is a sequential shift register with combinational logic that causes it to pseudo-randomly cycle through a sequence of binary values.
FIG. 1 reproduces FIG. 2 of U.S. Pat. No. 5,550,843 by Wilson K. Yee entitled ‘Programmable Scan Chain Testing Structure And Method’. The above-mentioned circuit comprises a programmable multiplexer for sequentially connecting columns of logic cells to enable the configuring of logic cell columns into one or more scan chains. Each column of logic cells contain an edge cell comprising a multi-input multiplexer, one of the multiplexer inputs being dedicated to receiving a signal from an adjacent cell, other inputs being connected to gate array input pads. A programmable control signal on the multiplexer enables the column to either receive test data from one of the gate array input pads or to connect as part of a scan chain by receiving a wrapping signal from the output logic cell of an adjacent column.
The aforesaid prior art solves a major testing issue of FPGAs and other programmable devices, but the cost paid in terms of silicon hardware is too expensive. For each logic cell cluster, the above patent proposes to have dedicated scan multiplexers and routing resources. Seeing the complexity and size of today's FPGAs, the number of such multiplexers will grow drastically which would further occupy valuable silicon space. Furthermore, the testing hardware, causing increased size, is never used by an actual user application. As small size and low power are a key universal selling point for today's electronic products in general and FPGAs in particular, the prior art looses its significance.
The testability offered by the aforesaid US patent covers only the logic portion and not the routing, which takes around 80% of total silicon size, and is hence more susceptible to failure.
Another drawback is that it is highly dependent on the correctness of EDA software tool set. As the programmable scan chain is activated through proper configuration of latches done using FPGA software and hardware, any small problem in setup may lead to wrong results.
Thus the major problem faced while testing an FPGA chip is its heavy dependency on system EDA software. Neither results/outputs can be expected nor inputs can be applied to the FPGA unless the Input/Output Block IOs and Logic blocks are programmed. This system proposes to remove this dependency of testing from software and yet give initial health check of the device on reset state of configuration latches. The implemented logic will help generate pseudo-random sequences without any need for user to program configuration latches.